This invention relates in general to semiconductor technology, and in particular to semiconductor devices and their manufacture.
In a conventional vertical MOSFET (metal oxide semiconductor field effect transistor) device, it is desirable to minimize the drain-to-source resistance or RDS(on) of the device. RDS(on) is proportional to the amount of power consumed while the MOSFET device is on so that reducing RDS(on) reduces the amount of power consumed by the MOSFET device. RDS(on) could be reduced by increasing the dopant (or carrier) concentration in the drift region of the device. However, it may not be desirable to increase the dopant concentration, because increasing the dopant concentration reduces the breakdown voltage of the device. Conversely, the carrier concentration in the drift region of the MOSFET device cannot be reduced to increase the breakdown voltage without also undesirably increasing RDS(on).
U.S. Pat. No. 5,216,275 describes semiconductor devices with increased breakdown voltages and improved on-resistance properties. The devices of the type described in this patent are referred to as xe2x80x9csuperjunctionxe2x80x9d devices. Each of the described superjunction devices comprises a composite buffer layer. The composite buffer layer has alternating doped P and N regions that are charge balanced. According to the scientific literature, superjunction transistor devices exhibit 5-100 times lower specific on-resistance (Ron,sp) than conventional high voltage MOSFET devices.
While such superjunction transistor devices exhibit high breakdown voltages and low on-resistance, they are difficult to manufacture. For a superjunction device to function properly, the alternating P and N doped regions in the composite buffer layer must be doped with the same amount of charge material to achieve a perfect charge balance. This is difficult to achieve in practice. See, for example, Shenoy et al., xe2x80x9cAnalysis of the Effect of Charge Imbalance on the Static and Dynamic Characteristics of the Super Junction MOSFETxe2x80x9d, Proc. of the ISPSD ""99, pp. 95-98, 1999. In addition, because it is extremely difficult to precisely balance the doping in the composite buffer layer of a superjunction transistor device, the practical maximum electrical field achievable in the composite buffer layer is limited to approximately 2xc3x97105 V/cm. The practical maximum electrical field achieved by a superjunction transistor device limits its breakdown voltage.
It would be desirable to provide for an improved semiconductor device that is less difficult to manufacture and that has a higher breakdown voltage and a lower on-resistance than the superjunction devices described above.
Embodiments of the invention are directed to semiconductor devices and methods for making semiconductor devices.
One embodiment of the invention is directed to a semiconductor device comprising: a) a semiconductor substrate; b) a first region of a first conductivity type in the semiconductor substrate; c) a second region of a second conductivity type in the semiconductor substrate; d) a plurality of charge control electrodes, wherein each charge control electrode in the plurality of charge control electrodes is adapted to be biased differently than other charge control electrodes in the plurality of charge control electrodes; and e) a dielectric material disposed around each of the stacked charge control electrodes.
Another embodiment of the invention is directed to a field effect transistor comprising: a) a semiconductor substrate of a first conductivity type having a major surface, a drift region, and a drain region; b) a well region of a second conductivity type formed in the semiconductor substrate; c) a source region of the first conductivity type formed in the well region; d) a gate electrode formed adjacent to the source region; e) a plurality of stacked charge control electrodes buried within the drift region, wherein each charge control electrode of the plurality of stacked charge control electrodes is adapted to be biased differently than another charge control electrode in the plurality of charge control electrodes, wherein the plurality of stacked charge control electrodes is adapted to adjust an electrical field profile within the drift region of the semiconductor substrate; and f) dielectric material disposed around each of the stacked charge control electrodes.
Another embodiment of the invention is directed to a method for forming a semiconductor device, the method comprising: a) providing a semiconductor substrate having a first region of a first conductivity type; b) forming a region of a second conductivity type in the semiconductor substrate; c) forming a first charge control electrode; and d) forming a second charge control electrode, wherein the first charge control electrode is adapted to be biased differently than the first charge control electrode.
Another embodiment of the invention is directed to a field effect transistor comprising: a) a semiconductor substrate of a first conductivity type having a major surface, a drift region, and a drain region; b) a well region of a second conductivity type formed in the semiconductor substrate; c) a source region of the first conductivity type formed in the well region; d) a source contact layer coupled to the source region; e) a gate electrode formed adjacent to the source region; f) a charge control electrode buried within the drift region, wherein the charge control electrode is adapted to be biased at a different potential than the gate electrode or the source contact layer, and is adapted to control the electric field in the drift region; and g) a dielectric material disposed around the charge control electrode.
Another embodiment of the invention is directed to a method for forming a field effect transistor comprising: a) providing a semiconductor substrate of a first conductivity type having a major surface, a drift region, and a drain region; b) forming a well region of a second conductivity type in the semiconductor substrate; c) forming a source region of the first conductivity type in the well region; d) forming a source contact layer on the source region; e) forming a gate electrode adjacent to the source region; f) forming a charge control electrode within the drift region, wherein the charge control electrode is adapted to be biased at a different potential than the gate electrode or the source contact layer, and is adapted to control the electric field in the drift region; and g) forming a dielectric material around the charge control electrode.
These and other embodiments of the invention will be described with reference to the following Figures and Detailed Description.